Hi, 

I have CY8C6347FMI system and I need to communicate with ICs in both 3.3V and 1.8V domains. Can I do it without level shifters, just by providing diffenet  voltages to two different IO domains?

Hello, I am new to the psoc product. I'm trying to use a distance sensor. The firmware does not work as it should and I do not know if it is the fault of a faulty sensor or software errors. The sensor is connect correctly (the pins are exactly the same as in the psoc wizard). The sensor shows a random value and does not refresh it until I lift the object (large cardboard) above the sensor, I put it in another place in the plug, a different value is displayed, not similar to the real one. Can someone please help me?

Customer application where he is relying on ARM when power off GPIO will be in HiZ state.

Two cases to this to consider, Power disconnected (switch opens to PSOC Vdd) or power collapses,

such as in a transformer fed simple bridge > regulator PSOC, where PSOC power pin is always "in circuit,

connected".

Ap notes do not discuss this. I stated to customer than when Vdd drops below its min datasheet spec  value

all bets are off as to what a GPIO pin looks like. That there is possible charge trapping inside device driving gate 

that would have to bleed off to make sure a device, in this case the NMOS side of totem pole, and that could take a 

long time.

Question, what is the state of a GPIO pin, and can it be controlled, pre destined, when Vdd drops below operating

datasheet spec value ? I think answer is NO !

Regards, Dana.

Hi,

I am trying to use the IDAC component in the PSoC 4 BLE. When I let the PSoC Creator auto-assign the pins during build, it assign the pin P2.7 [44] to the iOut which is unavailable on the board. I have assigned it to a analog pin (p0.0) but it doesn't work correctly and displays the following message:

"Function CSIDAC8.iout is reachable through the analog routing fabric, but using this pin may lead to routing congestion or failure."

I don't know if the problem is because of the pin I assigned or another thing I've done in the project?

Thank you

hi,

i found  a problem  using the rx hw fifo buffer,

if i read a byte from the fifo and in that exact time anew byte is recived the data i read i corrupted.

is there any way to read the fifo without that problem?

thanks.

当我使用CYP15G0101DXB这块芯片与FPGA进行数据交互时，发现CYP15G0101DXB发送给FPGA的RXCLK信号质量较差，因此FPGA无法利用该时钟信号对数据进行解析。

CYP15G0101DXB与FPGA并不在一块板卡上，带有FPGA的板卡通过接插件扣插在带有CYP15G0101DXB芯片的板卡上，发送与接收的传输速率设置为1250MBaud，但是将速率降低为800M或200MBaud时便能够收发正常。

请问当CYP15G0101DXB传输速率为1250Baud即RXCLK时钟为125MHz时，经过接插件信号质量就会变差吗？

Hello all,

I'm working on controlling LED with NEC remote control and Capsense(Using custom PCB with PSoC4 MCU cy8c4245axi-483). My Project which I have attached here is work fine with either through remote or Capsense button. As Problem is different from previous one, I have already opened thread regarding this issue. but problem has not been solved .https://community.cypress.com/t5/PSoC-4-MCU/IR-interfacing-with-Capsense-Button/m-p/273105/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufEtOOU5IQ0I4UkVBUUkzfDI3MzEwNXxTVUJTQ1JJUFRJT05TfGhL#M39362 .

Please Note that I wanted to operate LED by both the ways. Here I am attaching my Project(in which it is working only with CapSense)

#include "project.h"
#include "stdio.h"
#define TIMER_FREQUENCY 1000000UL
#define ADDRESS_SIZE    16U
#define DATA_SIZE       16U

volatile uint16_t timeStart;
volatile uint16_t timeEnd;
uint32_t pulseWidth;
volatile uint16_t pulseReceived;
volatile uint16_t overflow;
uint32_t timeDiff;
/******************************/
uint8_t startFrameFlag = 0;
uint8_t addressCount = 0;
uint8_t dataCount = 0;
uint16_t address_temp;
uint8_t address_temp2;
uint8_t address;
uint8_t address_inv;
uint16_t data_temp;
uint8_t data;
uint8_t data_inv;
uint8_t frameReceived;
unsigned char status=0;
unsigned char prev_status=0;
unsigned char flag[10];
/*****************************/
typedef enum 
{
    IDLE,
    ADDRESS_FRAME,
    DATA_FRAME,
}state;
state nec_state;
volatile uint16_t countFlag;
uint16_t timerPeriod;
asm (".global _printf_float");
int _write(int file, char *ptr, int len)
{
    (void) file;
    int i;
    for (i = 0; i < len; i++)
    {
        UART_UartPutChar(*ptr++);
    }
    return(len);
}
void Pin_ISR();
void Timer_ISR();
void DecodeProcotol(uint16_t pulseWidth);
CY_ISR(Pin_ISR)
{
    uint8 intrSrc;
    intrsrc=NEC_IN_ClearInterrupt();
    if(intrSrc != 0u)
    {
        if(countFlag == 0)
        {   
            timeStart = Timer_ReadCounter();
            countFlag = 1;
        }
        else
        {
            timeEnd = Timer_ReadCounter();
            pulseReceived = 1;
        }
    }
}
CY_ISR(Timer_ISR)
{
    if((Timer_GetInterruptSourceMasked() & Timer_INTR_MASK_TC ) != 0)
    {
        if(countFlag != 0)
        overflow++;
        Timer_ClearInterrupt(Timer_INTR_MASK_TC);
    }
}
void DecodeProcotol(uint16_t pulseWidth)
{
    uint8_t bit = 0;
    switch(nec_state)
    {
        case IDLE://Checks for start of frame
        {
            if(pulseWidth > 12000 && pulseWidth < 15000)
            {
                nec_state = ADDRESS_FRAME;
                startFrameFlag = 1;
            }
            else
            {
                //Invalid Frame received
                nec_state = IDLE;
            }
        
            break;
        }
        case ADDRESS_FRAME:
        {
            if(pulseWidth > 1100 && pulseWidth < 1160)
            {
                bit = 0;
            }
            else if(pulseWidth > 2200 && pulseWidth < 2300)
            {
                 bit = 1;
            }
            address_temp |= ( bit << addressCount);
            addressCount++;
            if(addressCount >= ADDRESS_SIZE)
            {
               addressCount = 0; 
               nec_state = DATA_FRAME;
            }
            break;
        }
        case DATA_FRAME:
        {
            if(pulseWidth > 1100 && pulseWidth < 1160)
            {
                bit = 0;
            }
            else if(pulseWidth > 2200 && pulseWidth < 2300)
            {
                bit = 1;
            }
           data_temp |= ( bit << dataCount);
           dataCount++;
            if(dataCount >= DATA_SIZE)
            {
               dataCount = 0; 
               nec_state = IDLE;
               frameReceived = 1;
            }
            break;
        }
    }
}
int main(void)
{
    CyGlobalIntEnable; /* Enable global interrupts. */
    CapSense_Start();
    CapSense_InitializeAllBaselines();
    CapSense_ProcessAllWidgets();
    CapSense_ScanAllWidgets();
    Pin_Interrupt_StartEx(Pin_ISR);
    Timer_Interrupt_StartEx(Timer_ISR);
    UART_Start();
    UART_UartPutString("Working\r\n");
    nec_state = IDLE;
    Timer_Start();
    timerPeriod = Timer_ReadPeriod();
    /* Place your initialization/startup code here (e.g. MyInst_Start()) */
    for(;;)
    {
            countFlag = 0;
            timeEnd = 0;
            timeStart = 0;
            frameReceived = 0;
            address_temp = 0;
            data_temp = 0;
            address_inv = 0;
            address = 0;
            data_inv = 0;
        if(pulseReceived)
        {
            if(timeEnd > timeStart)
            {
                timeDiff = (overflow * timerPeriod) + (timeEnd - timeStart);
            }
            else
            {
                timeDiff = (overflow * timerPeriod) - (timeStart - timeEnd);
            }
            timeStart = timeEnd;
            overflow = 0;
            pulseReceived = 0;
            pulseWidth = timeDiff; //in uS
            //printf("%u uS\r\n", pulseWidth);
            DecodeProcotol(pulseWidth);
        }
        if(frameReceived)
        {
            address_inv = address_temp >> 8;
            address = address_temp & 0x00FF;
            data_inv = data_temp >> 8;
            data = data_temp & 0x00FF;
                if((uint8_t)(~data) == data_inv)
                {
                    //printf("Data received: %u\r\n", data_temp);
                    printf("Data received: %u\r\n", data);
                }
                else
                {
                    printf("Data corrupted\n\r");
                }
        }
            if (CapSense_NOT_BUSY == CapSense_IsBusy()) {
            CapSense_ProcessAllWidgets();
            status  = CapSense_IsWidgetActive(CapSense_BUTTON08_WDGT_ID) || data==18;
            if (status && !prev_status) {
                if(flag[8]==0)// && (OF_1_Read()==1))  
                    {flag[8]=1;OF_8_Write(0);
                    }
            else
                    {flag[8]=0;OF_8_Write(1);
                    }
            }
            prev_status = status ;
            CapSense_ScanAllWidgets(); }
    } 
}

. Please Have look. Your suggestions are always helpful for me.

Thanks & Regards,

Prem KB

@MotooTanaka @Hari @JoMe_264151 @BragadeeshV 

Hello

In the datasheet for the PSOC4 timer component (TCPWM_P4_v2_10) There is a statement concerning the reload input:

"For all devices, except PSoC 4000, PSoC 4100, PSoC 4200, it should only be used when the counter is not running."

Does this exception apply to all of the 4000, 4100, and 4200 series? For example is the "4100S" series also included in this exception? What are the consequences of violating this condition? What is the recommended workaround for this?

Thanks

BoB

I'm just starting to look at PSoC 6 after working with 4 for quite a while, and I can't get past this first issue.

There is another post about this, along with a comment saying "we don't have this issue, it's likely to do with the pin configuration."

So I've created a new empty project in PSoC Creator, for a CY8C6247BZI-D54 ... I've put a single output pin on the schematic, and selected "Single-Sync" ... I've done nothing else and I get that warning.

I've experimented with different drive settings etc, but I can't get it to go away.

Similarly if I change it to an input pin (with hardware connection, and attach it to something like a status register) ... it's fine without sync, but with single or double-sync I get the same warning (well, InSyncNeeded.)

So I don't understand how everyone else isn't seeing this?

The family datasheets for the 4200L and the 62 family both contain the same section detailing the sync capability (PA Data Input Logic/PA Data Output Logic) ... so it's not a capability problem??

What am I missing?

Hello everyone,

I am developing at a very low level communication between the PSOC-4 and a SD card via SPI protocol. In this whole process I'm at the point where I need to transfer 514 bytes per SPI to the SD card (MOSI).

The concept is very simple but I have a lot of problems with increasing the data rate of the SPI block. The whole setup works fine below 1.5 Mbps, but when increasing to 4Mbps with oversampling at 16 (3Mbps real) the DMA transfer stops working properly. I have tried to narrow down the problem as much as possible and it seems that the problem is in the behaviour of the DMA block.

To rule out that there is no problem with the SPI block I have increased to 8Mbps data rate and used the CPU to communicate with the card and everything has been successful. I would like to remind you that at lower speeds of 1 and 1.5 Mbps everything works fine with the DMA. At first I have worked with these low frequencies to be able to analyse the communication with a logic analyser. My idea was, that once everything works fine, to simply increase to the maximum speed.

In order not to go into too much detail I can reduce the problem to a simple SPI transfer with DMA (forgetting that the communication is with an SD). I simply need to transmit 514 bytes of data over the MOSI line at over 3 Mbps.

The information flow is simple, once everything is ready, the DMA descriptor is validated and the channel is enabled to start the transfer to the FIFO register of the SPI module. The problem is that in the interrupt function that is indicated to the DMA it jumps with an error. The error produced is obtained with TxDMA_GetDescriptorStatus(0);. The normal behaviour is that the DMA generates an interrupt with that flag to CYDMA_DONE. Instead it generates two interrupts with the flag to CYDMA_INVALID_DESCR.

The weirdest thing is that it works at low data rates and doesn't work at high data rates. I think I'm missing something and I don't understand what.

The part of the code that involves this problem is first of all the initialisation:

struct DataPacket{
//    char token;
    char data[512];
    char CRC[2];
}__attribute__((packed));

struct DataPacket multipleWriteBuffer;


int main()
{
TxDMA_Start((void *)&multipleWriteBuffer, (void *)SPI_TX_FIFO_WR_PTR);
TxDMA_SetInterruptCallback(TxDMA_Done_interrupt);
CyIntEnable(CYDMA_INTR_NUMBER);
CyGlobalIntEnable;
.....................

The function to be triggered by the DMA interrupt is:

void TxDMA_Done_interrupt()
{
    descriptorStatus=TxDMA_GetDescriptorStatus(0);
    descriptorStatus=descriptorStatus & 0x00070000U;
    switch(descriptorStatus){
        case CYDMA_DONE:
        {
              DMAFlags=1;
        }; break;
....................................
        case CYDMA_INVALID_DESCR:
        {
            DebugPin_Write(0);
            InvalidDescriptor++;
            DebugPin_Write(1);
        }; break;
    }
}

when I need the to start data transfer:

        TxDMA_ValidateDescriptor(0);
        TxDMA_ChEnable();

The DMA descriptor configuration is:

The SPI advanced tap configuration is :

And less relevant to the case is the spi basic tab:

Conection between SPI and DMA module:

I think including an image of the logic analyzer may help to notice when the InvalidDescriptor event occurs. Remember that I have a debug pin that throws a pulse when this event occurs so I can detect it in the logic analyzer.

General view of the transmission, without zoom:

A zoom in on the area where these events occur:

In summary: every time I start a transfer, the interrupt with the CYDMA_INVALID_DESCR error is raised.

Do you have any idea what is going on?
Thank you for your help.