Hi,

How FX2LP control endpoint 0 can transfer more than 64 bytes?. The control center device info shows 64 bytes for the control endpoint 0. It is the hardware versus software limitation?.

I have many kitprog (ver1) from ther CY8CKIT-059,  These have been broken off from the kit.  The kitprog does not have connectivity to the SWD or JTAG pins, so the only method of programming the kitprog is by using the bootloader installed from the programmer.  As custom bootloader may resolve my issue below but I can't change the bootloader.

The issue is I can successfully bootload host a custom program many times successfully, but then later when adding functionality to the bootloadable program I get an bootloader host downloading issues that prevent downloading.

I am assuming the original kitprog has not been verified correctly and there is an incompatibility. I do have a couple questions that maybe someone can answer that has been though this issue,

I am using the kitprog hardware (not 2) with the latest software 2.2.1  The cy9ckit-059 says this needs to be 2.20 or later.  The documents for the original kitprog user manual (ver-I 2018) says the bootloadable needs to start its program at 0x0002800.  However the newest kitprog2 user manual has the starting address for bootloadables at 0x0003200.  Is it possible to findout the flash size of the locked part for kitprog and kitprog2?

This value is need to use the kitprog for custom applications, but only cypress has accessibility to the kitprog and kitprog2 source.

Brian

Hi all

For infineon+CYPRESS people.

Are there any plan for releasing PSOC 4200L prototyping kits.

I vote for it😊

Regards

Luis

Hello I have the kit cy8ckit-050 Psoc 5lp. I recently replaced a computer and I am unable to connect the kit to the new computer. I would love to help, I'm on the verge of despair. Thank you.

I'm trying to adapt this code example to our design requirements. We are currently running this code example on PSoC 6 BLE prototyping kit (CY8CPROTO-063-BLE). I've switched the BLE stack to running on Cortex M0+ following the instructions and changed the toolchain to MDK. However we encounter HardFault during App2 startup, in the Cy_BLE_Start function. Our observations are:

1. This issue does not occur when using ARM-GCC toolchain
2. App1 (DFU mode) works properly
3. With the debugger we were able to trace down the HardFault to function Cy_BLE_StackInit, and from the stack frame the PC register address when the fault occurred belongs to the function CyBle_RcbRegRead
   

   0x10016588   0x00000028   Code   RO        10367    i.CyBle_RcbRegRead  cy_ble_stack_mdk_controller_soft_cm0p.a(CyBleRcb.o)​

Any help would be appreciated. Thanks!

I want to run a behavioral simulation of S29GL01GP.The secotor had been erased，and programed in word mode.But the data which be read from flash is 16'hXX2X.AS shown in the follow picture:

What‘s wrong in this timing sequence?

Hi all

Our FPGA may send variable length data(4B~16kB, integral multiple of 4Bytes) to FX3 in which firmware runs as slave FIFO mode, host app invoke XferData() to initiate a BULKIN transfer for reading data stored in FX3.

At each BULKIN event initiated by host, a certain len parameter must be passed into XferData() refer to Cypress CyAPI Programmer's Reference, for example 16384, if actual length of packet which sent by FX3 is shorter than 16384(ie partial packet), will XferData() receive the short length packet and return ture or return false for time-out? if this function can receive short packet, where can i get the actual length after the XferData() executed ?

Is it possible to change the RSSI of bluetooth?

I think it is possible to get it with "wiced_bt_dev_read_rssi()", but I couldn't find the function to set it.