Hi 

I have a custom board with CYUSB3014-BZXC interfaced with Xilinx ultrascale  fpga for which I am facing some issue with gpif interface. I have the a working gpif inteface on a previous board in which  CYUSB3014-BZXC is interfaced with Xilinx artix fpga. In the new board with ultrascale , i am reusing the fx3 image and the fpga code ( fx3 interface part is same). However when I do a slave read with GPIF interface , I see that the FX3 is not receiving the data from the FPGA. I have probed on the data lines and pclock  signals. Clock is fine at 100MHz and data is also coming out of the FPGA. Other signals like SLCS, SLWR,SLRD,address , pktend etc are also in their expected state. I am doing a 16384 length transfer and the watermark is kept at 16380. However i note that both FlagA and FlagB are staying high throughout and not going to 0. I have a doubt that the Fx3 fifo pointer is not getting incremented or the GPIF state machine is somehow stuck. I do not have access to UART pins. They are connected to the FPGA. Any pointers as what might be happening will be really helpful.

Thanks and regards

Nithin

Hi, 

(How) Is it possible on PSoC5LP to DMA transfer 32 bytes from DWT_CYCLE_COUNT 0xE0001004 to RAM.

Viktor

Hi,

We are using Cypress 43455 (murrata 1MW) with NXP MCU with Wiced SDK. We are trying to connect wifi module with a wifi router configured in AC only mode but are not able to do so. We are able to scan the router but join attempts to the router always fails. We have observed that if we set the country code as USA on the module side we are able to connect to router.

We have tried to make sure that the country selection on router and module match but we don't see any success. We are able to use all the other modes (N, A, mixed etc) with other country code but not AC.

What could be the solution for this? We want to set the country code as UK and run AC mode. What are we missing here?

Firmware and CLM blob information:

Regards

Dear community,

I have to implement a virtual COM with the FX3 as an alternative to the UART module for the cyfx3s_fatfs example; so I need a set of API similar to CyU3PUartReceiveBytes and CyU3PUartTransmitBytes and the possibility to write buffer with DMA (as in cyfx3s_fatfs) but working through an USB Virtual COM.
I started working with UsbUart example by modifing the DMA configuration and sockets (in attached) to use the "void CyFxUartSendBuffer(uint8_t *Buffer_Print,uint8_t cnt_read)" function, but without results.
Please, someone could give me some ideas or code example?
Consider that is my first time with this MCU, this architecture and in general with the USB.

Many thanks in advance, regards,
Corrado90

I made a custom board consisting of a CYPD3125 controller.

The board shall be the preferred power supply to a tablet connected via USB type-c. In case the boards external supply is down the tablet shall power the board. So the board with the CYPD3125 must be either source or sink.

The firmware is based on the notebook project that has already all main functions.

Now the problem is that the producer FET is never turned on. I only measure ~150mV.

Does anyone have an idea?!

Please find the attached screenshot of the schematic.

Hi, 

I am new to development on the Cypress/PSoC platform. I will attempt to explain what I am trying to do. I have initialized an IDAC source and connected its output to the input of an analog MUX. The analog mux has two outputs, each of which is connected to an analog pin. Upto here, my operation works fine and I have managed to configure and test these components. 

Now I want to connect the two analog output pins from the MUX to a SAR ADC. I am using the component - Sequencing SAR ADC [v2.10]. I am trying to configure it with two single-ended channels and attempting to feed the input of the two analog pins from this to the inputs of the ADC. However, when I try to do this, it gives me 3 errors and a couple of warnings. I will attach a screenshot of these errors so that it can be understood what the issue might be. Any assistance on this will be appreciated. 

I would like to use a PSoCLP5 as a "power manager" for a large Xilinx FPGA.  The PSoC5LP controls the sequencing of power supplies to the FPGA, monitors current and output voltage of every FPGA supply rail, temperature, etc. 

All of these measurements are reported over I2C to the FPGA and via a USB to UART bridge (implemented in the PSoC5LP) to a host system.  All of these requirements make the PSoC5LP a very good solution.

The PSoC5LP is powered continuously from a switching regulator that runs slightly above the dropout voltage of two LDOs.  One of the LDOs produces +3.3V for most of the I/O and VDDA.  VDDA is powered though a LC filter.  The other LDO produces 1.8V for producing one of the I/O banks VDD. 

Driving an unpowered FPGA will forward bias the ESD diodes on its inputs causing a voltage to appear on its power supply rails.  Unless the generated voltage is kept below 2.5V when the FPGA is not powered, the Xilinx device may be damaged.   One robust solution is to run the I/O between the PSoC5LP and the FPGA at 1.8V.  

Here are a few questions:

1. Are there any power sequencing requirements among the PSOC5LP's power supply rails?

2. If an I/O bank is not in use is it safe to remove power for that bank?  Will the rest of the PSoC5LP I/O on other banks continue to function normally?

Thanks for your help,

Wayne

Hi All - 

I'm not 100% certain that this is the right location for this discussion, so my apologies if it is not.

I'm trying to understand how the USB PD specification requires the handling of a situation where a PD Source offers a power rating in one of its PDOs that is higher than a PD Sink requires.   

For example, in my application I'm considering configuring my CCG2 with the following Sink PDOs: 

• 5V@3A  [15W], 
• 9V@2.8A  [25.2W], 
• 15V@1.8A  [27W].

My application uses a charger that would likely draw 2.64A@9V  or 1.66A@15V .   At 5V my charger would like to draw 3.6A, but the charger is limited to an input current of 3.3A, so I think a 3A PDO limit is fine as I'll software limit the charger.

My confusion is how the CCG2 will negotiate with various off-the-shelf chargers that are available on the market.   For example, the Nintendo Switch and Apple MacBook chargers offer the following PDOs:

Switch:

• 5V@1.5A [7.5W]
• 15V@2.6A [39W]

MacBook:

• 5.2V@2.4A [12.5W]
• 9.0V@3A [27W]
• 14.5V@2A [29W]

Now, when I plug my device into the Switch charger, which of my configured PDOs will it default to?  My highest PDO power draw is 27W, so will the Switch output my requested 15V@1.8A or will it provide me with 9V@3A which seems to be a standard 27W supply... 

The same question happens for the MacBook charger.   If I plug that into my device, then which PDO will be negotiated?

Let's also assume that my highest PDO option was actually 15V@2A instead of 1.8A for a power draw of 30W.  In that case, would the Switch negotiate 15V@2A even though that isn't one of the listed PDO that it offers?  And the MacBook charger... What would that output?

Hopefully this information will be useful to others as well.  I can't seem to find clear examples of these negotiations anywhere else.

-Shane