Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
Hello Infineon Experts,
We use a CX3 and one or two related image sensors on our board, and we are facing a CY_U3P_ERROR_FAILURE value returned by the...
Hello Infineon Experts,
We use a CX3 and one or two related image sensors on our board, and we are facing a CY_U3P_ERROR_FAILURE value returned by the CyU3PMipicsiSetSensorControl() API. This behavior is random, but the error rate is over 20 %.
We probed the I2C bus and some other significant signals (CX3_RESET*, CX3_XRESET and CX3_XSHUTDOWN), to look what’s happen (see attached pictures):
On successful execution, a first reading of Register 0x0012 (CY_U3P_MIPICSI_REG_GPIOIN) is done, bits [2:1] of this value are set to ‘1’ to drive High XRESET and XSHUTDOWN pins, the changed value is written to Register 0x0014 (CX3_CSI_SENSOR_SIG_VAL) and a second reading of Register 0x0012 is performed to be sure that Register 0x0014 is correctly written. So, reserved bits of Register 0x0014 are preserved as requested to section 1.10.7 of CX3 TRM.
On fail execution, the second reading of register 0x0012 doesn’t match the writing to Register 0x0014 and the CyU3PMipicsiSetSensorControl() API returns CY_U3P_ERROR_FAILURE. The difference concerns the reserved bit 0.
Do you have an explanation for this error CY_U3P_ERROR_FAILURE?
For your information, both SDA and SCL signals are pulled high with 2kΩ resistors, and the I2C block is initialized (by calling CyU3PMipicsiInitializeI2c() API) before initializing the MIPI-CSI-2 block (i.e. before calling CyU3PMipicsiInit() API).
Hyperflash is not responding to any commands except status register read. I tried word programming , buffer programming, sector erase, Chip erase, Dev...
Hyperflash is not responding to any commands except status register read. I tried word programming , buffer programming, sector erase, Chip erase, DeviceID reading but none of this worked. Everytime status register value remains 0x80.
Hello! My team and I are working on a project that involves a portable, handheld device and a custom made docking station for that device. The porta...
My team and I are working on a project that involves a portable, handheld device and a custom made docking station for that device. The portable itself will contain hardware that will generate a 2-lane DisplayPort video signal that we would like to output over USB-C to our docking station that will then convert the video to HDMI before going to a normal monitor/TV.
My question is whether or not the example "CCG2 Type-C to DisplayPort" reference design is a good design to follow. It seems as though that design is taking a USB-C input, handling the Alt Mode and Billboard handshaking, and then outputting a DisplayPort signal. We want the opposite - a solution acts as a DisplayPort source to be transmitted over USB-C. Does Cypress have a solution like this that exists?
Our portable also has a LiPo battery that needs to be charged from this USB-C cable such that the portable is a DisplayPort source but a power sink. There aren't any cases where our portable would act as a power source that would supply power across the USB-C cable. I was hoping to use TI's TPS25750 to handle this USB PD negotiation, but I don't think that will work well with this DisplayPort Alt Mode ecosystem. Will the Cypress CYPD2119-24LQXIT be able to handle these PD negotations on top of handling the DisplayPort Alt Mode?
Please let me know if this doesn't make sense and I can absolutely provide more information.
I am confused by the classification of CYBLE-416045 and EZ-Serial Support. Older posts (2019) claim there is no intention for CYBLE-416045 to support...
I am confused by the classification of CYBLE-416045 and EZ-Serial Support. Older posts (2019) claim there is no intention for CYBLE-416045 to support EZ-Serial and I do not see this among listed devices in documentation claiming such support, yet the CYBLE-416045-EVAL I purchased is listed as an EZ-BLE and documentation which comes with the kit references EZ-Serial. Can you please clarify the standing of this module. If there is no intention to make this module support EZ-Serial, what is the closest module to it that does (eg, Bluetooth 5 support, number GPIOs, etc.)
I need to achieve low standby power consumption in a system with an FX3 and a Xilinx FPGA. This system primarily remains in a low power idle state fo...
I need to achieve low standby power consumption in a system with an FX3 and a Xilinx FPGA. This system primarily remains in a low power idle state for 99% of the time where neither the FX3 or FPGA is being used.
Referring to the block diagram below, the PSoC is powered continuously through the LDO. The PSoC controls switching regulators that power a USB host, the FX3 and the Xilinx. The PSoC also performs aggressive power management to maximize battery life.
The PSoC turns on power to the FX3 and the Xilinx FPGA. All of the FX3's core VDD(x) and IO VIO(x) supplies are powered. The FPGA's IO banks connected to the FX3 are powered as well to avoid the FX3 driving an unpowered FPGA or vice versa.
Later, the PSoC will apply power to the USB Host system which in turn powers VBUS on the USB connector. VBUS is used to hold the FX3 in RESET (using an RC network) until VBUS is stable.
1. Will this method of powering the FX3 work?
2. I'm confused about the use of VBATT versus VBUS FX3 signals. The Super Speed Explorer connects VBUS on the USB connector to the FX3's VBUS signal. The FX3's VBAT signal is not connected on the SSE. The FX3 DVK connects a select-able power supply(+5V,+3.3,+2.5) voltage or a battery through a diode OR to the FX3's VBAT signal. VBUS from the USB connector is connected to the FX3's VBUS signal. Other FX3 based boards connect the VBUS line from the USB connector to both VBAT and VBUS on the FX3. I'm not sure what is the correct usage for my application. Please explain.
3. I have other H/S USB devices that would share one USB Gen 3 connector. It is possible to insert a CY7C65642 USB hub on the D+ and D- signals?
I want to configure the DS-1 port of CY611 EZ-USB HX3PD EVK to supply 12V. But when I try to configure using EZ-USB HX3PD configuration ...
I want to configure the DS-1 port of CY611 EZ-USB HX3PD EVK to supply 12V. But when I try to configure using EZ-USB HX3PD configuration Utility - PD Controller- Port 1, it shows me error - Atleast one 5V PDO should be enabled in Source PDO. But if add another source PDO of 5V, it does not save the configuration.