I am trying to compile a C/C++ makefile project using the Eclipse IDE for ModusToolbox (Version:  2.2.0, Build ID: 2181) for CY8CKIT-062-BLE  target.  I am able to compile  *.c and *.cpp files but *.cc files  is excluded from the compilation.

If I add following in the Makefile:

SOURCES = $(wildcard extlib/*.cc) 

The build console displays following error message:

../mtb_shared/core-make/latest-v1.X/make/core/build.mk:386: *** Incompatible source file type encountered while constructing explicit rule: extlib/utils.cc. Stop.

Hello,

I am using PSOC6 PROTOTYPEKIT BOARD 。
I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3
The Screenshot in PSOC Creator 4.3.

The errors occurred in building
It seems that the PSOC Creator 4.3 cannot interpret the line 171

Can't handle expression 'Z' in the final equation for 'org_data(0)'.

And I do not know how to solve it.

And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.

Thanks in advance.

HI,

        I bought a CYBLE-013025-EVAL , and it includes CYW20737 silicon device .  I saw the datasheet of CYW20737  mentioned it supports "Bluetooth Smart Audio", and details can  available in application notes on this topic. However, I can't find related application notes  introduce how to implement this function by SDK(WICED SMART). Does there has application notes about how to implement Bluetooth Smart Audio?

Thanks

Best regards

 I tried creating a project for the CY8C6245 processor on PSOC Creator 4.4.

  It is not in the list of allowable processors.  The PSOC 62 processor version  246 and 247 parts are there, but not the 245.

  What can I download to support the CY8C6245 on PSOC Creator?

Hi

I am trying to use IPC to share 2 variables between M4 and M0. I am able to share a single variable, now I need to share 2, one of them is an array (buffer for UART).

I can't find app-notes for this task. Do you have any advice ?

thanks

I'm trying to use the ShiftReg 2.30 component in the schematic editor.   I'm looking for a output "pin" to tell me if the input FIFO is empty, so I can stall the clock, at least that's how I'm thinking about it.   

The datasheet has a statement saying The Load operation has the hardware restriction that the load event can be provided only when input FIFO is not empty.   It seems unclear to me what happens if the Load input is asserted when the FIFO is empty.   

Since the only output other then ShiftOut is the Interrupt signal, I'm guessing that might be it, but I'm looking to use it in additional UDB logic, rather than feeding it to the interrupt controller.    Can anyone provide more guidance, or a working example link.   

Note: An earlier form posting related to using DMA with ShiftReg seems like it might be relevant, but the link to it seems broken.