I'm having difficulty figuring out how to get my EZ-USB FX3 GPIF-II synchronous master interface working reliably.

For each of the following questions I only want to know the answers that apply to the EZ-USB FX3 when operating the GPIF-II in synchronous master mode.  I don't care about synchronous slave mode or asynchronous modes.

1. What are the minimum and maximum allowed PCLK frequencies?
2. When executing CyU3PPibInit() what are the minimum and maximum functional clkDiv values for the PibClock?
3. When executing CyU3PPibInit() should isDllEnable be true or false, or does the answer vary based on clkDiv?
4. Do I need to configure the PIB DLL CTRL register (0xE0010028), either directly or via CyU3PPibDllConfigure()?
5. In pib_regs.h the HIGH_FREQ bit includes the comment "0: 23-80MHz, 1:70-230MHz".  Does this mean the PIB DLL CTRL register should only be used for the 23MHz-230MHz frequency range?
6. Various phase selects are defined in pib_regs.h (CORE_PHASE, SYNC_PHASE, OUTPUT_PHASE) and used by CyU3PPibDllConfigure().  Why are these fields not defined in EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. F?

Hi,

I'm using ADC component of CYBLE-416045-02 MCU. I have 4 analog pins which needs to be attached on 4 separate ADC channels but its showing me analog internal routing error. For the time being I'm using an internal mux like shown in the picture, but i want to use 4 different  channels of the ADC and not through internal mux.Please help.

Hi All.

Our customer going to make Audio device through CYBT-343026-01.
Can i embody A2DP in the Non-OS through CYBT-343026-01?
And Can distribute with Firmware form possible?

Please check this question.

Thank you.

Hello

I am testing CX3 with a certain sensor (100fps).

MIPI Setting is below

we have three problem.

1. Broken image

Image is broken line by line. 

2.  CB Failure

==================

AplnStrt:SMState = 0x1
TimeDiff = 10105 ms FPS = 98
TimeDiff = 10005 ms FPS = 99
TimeDiff = 9996 ms FPS = 100
TimeDiff = 9996 ms FPS = 100
TimeDiff = 9996 ms FPS = 100
TimeDiff = 10006 ms FPS = 99
TimeDiff = 9996 ms FPS = 100
TimeDiff = 9996 ms FPS = 100
CB failure
AplnStop:SMState = 0x5
AppStart

AplnStrt:SMState = 0x1
TimeDiff = 10046 ms FPS = 99
CB failure
AplnStop:SMState = 0x5
AppStart

AplnStrt:SMState = 0x1
TimeDiff = 10045 ms FPS = 99
TimeDiff = 9995 ms FPS = 100
TimeDiff = 10005 ms FPS = 99
CB failure
AplnStop:SMState = 0x5
AppStart

AplnStrt:SMState = 0x1
TimeDiff = 10045 ms FPS = 99
TimeDiff = 9995 ms FPS = 100

================================

Sometimes "CB failure" was happened. 

Can you advice me about the solution for fixing this problem?

I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM interface to 40MHz SPI signals and also 40MHz SPI signals sourced from the SPI F-RAM device to signals destined for the x8 parallel SRAM interface. As for the x8 parallel SRAM interface timings, conservatively, I have a memory address setup time of around 250ns, a memory address hold time of around 1250ns and a chip enable hold time of around 750ns ( I'm not quite sure of the timings right now and I know I am missing some timing information for some of the x8 parallel SRAM signals ). I plan on doing this with an ultra-low-power MCU, but, I'd need to use cycle-stretching on the Cypress F-RAM device(s). Is the above kind of conversion doable, especially the cycle stretching?

( N.B. The devices I want to use are one of these : https://www.cypress.com/file/444186/download , https://www.cypress.com/file/444186/download )

Thanks,

jdb2

Hello,

I am using PSOC6 PROTOTYPEKIT BOARD 。
I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3
The Screenshot in PSOC Creator 4.3.

The errors occurred in building
It seems that the PSOC Creator 4.3 cannot interpret the line 171

Can't handle expression 'Z' in the final equation for 'org_data(0)'.

And I do not know how to solve it.

And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.

Thanks in advance.

Hi Cypress,

Are there Errata sheets for S25FL064LABNFI043 & CYW43903KUBGT? 

Try to check on your website but unable to found it.

Dear Support team,

FRAM FM25V10 datasheet mentions that the device specifications are guaranteed over an industrial temperature range of –40°C to +85°C. But under maximum ratings section Ambient temperature range with power applied is mentioned to be –55°C to +125°C. I was wondering whether it is possible to operate this FRAM above 85°C upto 125°C?  Will it behave in the same manner as specified in the datasheet, in this case?

Thanking you in advance.

Hi,

I'm sure I'm doing something stupid, but I need some guidance. I downloaded the attached Cypress code from Github to implement a UART through the USB on CY8C4246AZI-L433. At this point in time, I'm just trying to use the communication to provide me with feedback about my hardware. So I've added a small amount of additional code to send strings of data, converted to ASCII. Currently that string is just fixed at the number 65535. What comes out at my PC (I'm using Terraterm, but I tried Putty as well) is usually just the first two digits. Maybe every 20 or 30 times, a larger portion of the string will come across. Any help would be appreciated. (And apologies in advance for my less-than-superhuman software skills!).

Windows 10, Creator 4.4, my own hardware.

Dave