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I'm trying to use the ShiftReg 2.30 component in the schematic editor. I'm looking for a output "pin" to tell me if the input FIFO is empty, so I ca...
I'm trying to use the ShiftReg 2.30 component in the schematic editor. I'm looking for a output "pin" to tell me if the input FIFO is empty, so I can stall the clock, at least that's how I'm thinking about it.
The datasheet has a statement saying The Load operation has the hardware restriction that the load event can be provided only when input FIFO is not empty. It seems unclear to me what happens if the Load input is asserted when the FIFO is empty.
Since the only output other then ShiftOut is the Interrupt signal, I'm guessing that might be it, but I'm looking to use it in additional UDB logic, rather than feeding it to the interrupt controller. Can anyone provide more guidance, or a working example link.
Note: An earlier form posting related to using DMA with ShiftReg seems like it might be relevant, but the link to it seems broken.
I am using the FM4-176L-S6E2CC-ETH with the Arm Developer Studio 2020.1-1 Gold Edition and I am having problems establishing a connection to the board...
I am using the FM4-176L-S6E2CC-ETH with the Arm Developer Studio 2020.1-1 Gold Edition and I am having problems establishing a connection to the board. The board has CMSIS-DAP Spansion V2.5. I also have the v14 CMSIS-DAP driver installed and the board shows up in my device manager under Ports as CMSIS-DAP Spansion Virtual Communications Port (COM 14). In Arm DS I open a New Debug Connection, associate it with the project for the board. On the connection tab I select CMSIS-DAP (SWD) and then click the Browse button on the Connection address. However, no connections are found. I am using Windows 10 with the latest updates.
I have the ST Discovery boards and can connect to them just fine so I am fairly sure my process is correct. I have use Keil uVision with the FM4-176L-S6E2CC-ETH before but I am migrating to the Arm DS.
Any suggestions on how to make the connection to the FM4-176L-S6E2CC-ETH boards?
I am using PSOC6 PROTOTYPEKIT BOARD 。I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well...
I am using PSOC6 PROTOTYPEKIT BOARD 。 I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3 The Screenshot in PSOC Creator 4.3.
The errors occurred in building It seems that the PSOC Creator 4.3 cannot interpret the line 171
Can't handle expression 'Z' in the final equation for 'org_data(0)'.
And I do not know how to solve it.
And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.
I developed a simple bootloader program using the kitprog2 with a hardware LED pulse. This successfully used the kitprog2 (one led) from an developme...
I developed a simple bootloader program using the kitprog2 with a hardware LED pulse. This successfully used the kitprog2 (one led) from an development kit. I am using creator4.4 and the kitprog2 (hardware) had been updated to kitprog3 software using the programmer 3.29. Basically the latest versions of all of the software, but with kitprog2 hardware.
I then decided to start another project based on the original kitprog that is attached to the cy8ckit-059. in order to make the "simpler" kitprog work I need to change the starting address for custom application code from 0x00003200 to 0x0002800 for the original kitprog verse the kitprog2 starting address. In addition the Bootloadable component needed to point the the elf and hex files that come with the 059 kit software. I built this and programmed using the bootloader host at the new address of host programmer F13B (verse F146 for KP2). I start a program using Active image "no change" for my new .cyacd file. This gives me the error "packet data invalid". After trying multiple options, I assumed that there was something incompatible with my approach, so I start a brand new project with just the simple example in the kitprog document and using the same 059 .elf and .hex files. This also has the same errors. At this point I go back to my original kitprog2 project and try and Bootloader host the newly built image2 and I now have the same error.
So to simplify this long story, I have a couple questions. If I follow the kitprog2 user manual, the kitprog2 was originally successful at loading the 2nd image "custom" as described in Kitprog2 manual, however when I follow the kitprog user manual for the older kitprog hardware (from 059 kit with KitProg 2.21) am I suppose to load the custom active image as "no change" using the *.cyacd generated in the build? This follow the kitprog user manual exactly except for selection of the "active application" is not described in the document or shown in figure 7-11
2nd question: Is the original kitprog on the 59 kit (software 2.21) still compatible with the newest bootloadable component in Creator 4.4.