Dear Yatheesh,

Sorry to bother you again.

After the last /RD signal problem was solved, no more underrun error.

But recently, all system combined test, I received error "No error : 18" from CY3014 uart port ,then, Xfer to FPGA failed.

Please kindly advise what is "No error : 18" ?

BR

Steven.

We want to control the output of the GPIO by changing the registers.
Is it possible to know the address of the register?

This is because we are using a dynamic test tool.

Thanking in advance.

Otsuki

Hello

  Please tell me how to configure I2S Driver with 2 Tx Channel and 1 Rx Channel.

  My chip : CYT4BF.

Thank you.

19200 x 1200, 100fps, MIPI 4lanes with 300MHz (600Mbps)

Setup is below

Error was happened with the massage which is "Min:99.959999~~".

So I tried to tune clock values but there was no effective values under 100MHz.

So I set values for 100MHz..

But There was error , "Max 100MHz".

For CX3, GPIF is not working on 100MHz, Is it right?

100MHz is maximum..but error was happened....Why?

Trying to network BLE devices configured in both central/peripheral roles.  A connection problem occurs (infrequently) whereby a peripheral will connect to a central device and then immediately disconnect (before CY_BLE_EVT_GAPC_SCAN_PROGRESS_RESULT is called).  Disconnect reason 62 is given.  Timing the connect / disconnect events shows there is ~140ms between them, and since the min/max connection intervals are set to 20/30ms on all devices, this suggests the peripheral/slave is not responding to the central/master connection attempts immediately after first connection.  The devices are very close together and there does not seem to be an rssi problem.  I've removed most additional code that I thought could be interfering with the timing of BLE event processing.  Any suggestion on what the problem might be and/or how to debug it?

ご担当者様

以下PCNの内容について確認させて下さい。

PCN205101

対象MPN：CY62146EV30LL-45ZSXI

対象MPN：CY62146GN30-45ZSXI

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From what I'm able to understand the "Bootloader application validation" option checks an 8bit checksum. This is not enough for my application since I need a proper CRC. The problem is that with an error in the flash there is a 1/256 chance of not detecting the error.

Is there a way to change this to a CRC16?

If there isn't a built-in option is there an example or application note explaining how to do this?

Basically, I would need to insert a CRC into the metadata as a linker step and then replace the "checksum check" in the bootloader with a CRC.

Hello,

I had another question regarding another post that I inquired about not long ago (link below):

https://community.cypress.com/t5/USB-Hosts-Hubs-Transceivers/HX3-Downstream-USB-3-0-to-Type-C-Receptacle/td-p/34438

For my application, I wanted to connect a USB Type-C receptacle to the CCG3PA for PD charging capability as well one of the downstream ports of the HX3 for USB 2.0/3.0 data. I originally wanted to retain legacy charging by connecting the Dp and Dm lines to both the CCG3PA as well as the HX3 since the CCG3PA has more charging profile capabilities. To reduce complexity, I decided to simply connect the Dp and Dm lines to the HX3 because BC1.2 and Apple Charging would suffice for the application. With this configuration, how would you recommend the downstream charging to be controlled considering that PD and legacy charging would be controlled by different devices? 

Could I do any of the following:

• Supply legacy charging through a USB charging switch and supply PD charging through the CCG3PA and tie the USB Type-C receptacle's VBUS to both?
• Connect the HX3's DS1_PWREN and DS1_OVRCURR to the CCG3PA gpios (with modified firmware) so that the CCG3PA can act as the charging switch for legacy charging?
• If neither of these would work, what is the best way to retain both USB2.0 data as well as legacy charging functionality with the configuration described above?

Thanks in advance!

Chris

dmaConfig.cb = CyFxUartLpDmaCallback

the CyFxUartLpDmaCallback can not be called for uart rx dma of mode when the rx receive data.The code is as follows：

CyU3PReturnStatus_t
CyCx3AppDebugInit (void)
{
CyU3PUartConfig_t uartConfig;
CyU3PDmaChannelConfig_t dmaConfig;
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;

/* Initialize the UART module */
status = CyU3PUartInit ();
if (status != CY_U3P_SUCCESS)
{
/* Error handling */
CyCx3AppErrorHandler(status);
}

/* Configure the UART
Baudrate = 115200, One stop bit, No parity, Hardware flow control enabled.
*/
CyU3PMemSet ((uint8_t *)&uartConfig, 0, sizeof(uartConfig));
uartConfig.baudRate = CY_U3P_UART_BAUDRATE_115200;
uartConfig.stopBit = CY_U3P_UART_ONE_STOP_BIT;
uartConfig.parity = CY_U3P_UART_NO_PARITY;
uartConfig.flowCtrl = CyFalse;
uartConfig.txEnable = CyTrue;
uartConfig.rxEnable = CyTrue;
uartConfig.isDma = CyTrue; /* DMA mode */

/* Set the UART configuration */
status = CyU3PUartSetConfig (&uartConfig, CyFxUartLpDmaCallback);
if (status != CY_U3P_SUCCESS )
{
/* Error handling */
CyCx3AppErrorHandler(status);
}

/* Create a DMA Manual channel between UART producer socket
and UART consumer socket */
CyU3PMemSet ((uint8_t *)&dmaConfig, 0, sizeof(dmaConfig));
dmaConfig.size = 16;
dmaConfig.count = 2;
dmaConfig.prodSckId = CY_U3P_LPP_SOCKET_UART_PROD;
dmaConfig.dmaMode = CY_U3P_DMA_MODE_BUFFER;
dmaConfig.notification = CY_U3P_DMA_CB_PROD_EVENT;
dmaConfig.cb = CyFxUartLpDmaCallback;
dmaConfig.prodHeader = 0;
dmaConfig.prodFooter = 0;
dmaConfig.consHeader = 0;
dmaConfig.prodAvailCount = 0;

/* Create the channel */
status = CyU3PDmaChannelCreate (&glUartRxChHandle,
CY_U3P_DMA_TYPE_MANUAL, &dmaConfig);
if (status != CY_U3P_SUCCESS)
{
/* Error handling */
CyCx3AppErrorHandler(status);
}

/* Set UART Tx and Rx transfer Size to infinite */
status = CyU3PUartRxSetBlockXfer(0xFFFFFFFF);
if (status != CY_U3P_SUCCESS)
{
/* Error handling */
CyCx3AppErrorHandler(status);
}

/* Set DMA Channel transfer size */
status = CyU3PDmaChannelSetXfer (&glUartRxChHandle, 0);
if (status != CY_U3P_SUCCESS)
{
/* Error handling */
CyCx3AppErrorHandler(status);
}

/* Initialize the debug application */
status = CyU3PDebugInit (CY_U3P_LPP_SOCKET_UART_CONS, 8);
if (status != CY_U3P_SUCCESS)
{
return status;
}

CyU3PDebugPreamble (CyFalse);

}

void CyFxUartLpDmaCallback (
CyU3PDmaChannel *chHandle, /* Handle to the DMA channel. */
CyU3PDmaCbType_t type, /* Callback type. */
CyU3PDmaCBInput_t *input) /* Callback status. */
{
CyU3PReturnStatus_t status;
gUartRecDataFlag = CyFalse;
if (type == CY_U3P_DMA_CB_PROD_EVENT)
{
/* This is a produce event notification to the CPU. This notification is
* received upon reception of every buffer. The buffer will not be sent
* out unless it is explicitly committed. The call shall fail if there
* is any application error. */

input->buffer_p.buffer[input->buffer_p.size] = '\0';
CyU3PDebugPrint (4, "%s", input->buffer_p.buffer);

status = CyU3PDmaChannelDiscardBuffer (chHandle);

if (status != CY_U3P_SUCCESS)
{
CyCx3AppErrorHandler (status);
}
}
}

The serial IO configuration is correct and the connection is correct. I've tested TX, Rx in register mode.Now I want to use DMA to receive data。but the the Callback function can not be called for uart rx dma of mode when the rx receive data.

Hi, 

I would like to know where I could get firmware and utilities for a CY7C65219 and CYPD5235  based dock solution using Goshen Ridge.