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From what I'm able to understand the "Bootloader application validation" option checks an 8bit checksum. This is not enough for my application since I...
From what I'm able to understand the "Bootloader application validation" option checks an 8bit checksum. This is not enough for my application since I need a proper CRC. The problem is that with an error in the flash there is a 1/256 chance of not detecting the error.
Is there a way to change this to a CRC16?
If there isn't a built-in option is there an example or application note explaining how to do this?
Basically, I would need to insert a CRC into the metadata as a linker step and then replace the "checksum check" in the bootloader with a CRC.
I have a custom board with CYUSB3014-BZXC interfaced with Xilinx ultrascale fpga for which I am facing some issue with gpif interface. I have the...
I have a custom board with CYUSB3014-BZXC interfaced with Xilinx ultrascale fpga for which I am facing some issue with gpif interface. I have the a working gpif inteface on a previous board in which CYUSB3014-BZXC is interfaced with Xilinx artix fpga. In the new board with ultrascale , i am reusing the fx3 image and the fpga code ( fx3 interface part is same). However when I do a slave read with GPIF interface , I see that the FX3 is not receiving the data from the FPGA. I have probed on the data lines and pclock signals. Clock is fine at 100MHz and data is also coming out of the FPGA. Other signals like SLCS, SLWR,SLRD,address , pktend etc are also in their expected state. I am doing a 16384 length transfer and the watermark is kept at 16380. However i note that both FlagA and FlagB are staying high throughout and not going to 0. I have a doubt that the Fx3 fifo pointer is not getting incremented or the GPIF state machine is somehow stuck. I do not have access to UART pins. They are connected to the FPGA. Any pointers as what might be happening will be really helpful.
I am using PSOC6 PROTOTYPEKIT BOARD 。I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well...
I am using PSOC6 PROTOTYPEKIT BOARD 。 I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3 The Screenshot in PSOC Creator 4.3.
The errors occurred in building It seems that the PSOC Creator 4.3 cannot interpret the line 171
Can't handle expression 'Z' in the final equation for 'org_data(0)'.
And I do not know how to solve it.
And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.
I bought a CYBLE-013025-EVAL , and it includes CYW20737 silicon device . I saw the datasheet of CYW20737 mentioned it supports "Bluetoot...
I bought a CYBLE-013025-EVAL , and it includes CYW20737 silicon device . I saw the datasheet of CYW20737 mentioned it supports "Bluetooth Smart Audio", and details can available in application notes on this topic. However, I can't find related application notes introduce how to implement this function by SDK(WICED SMART). Does there has application notes about how to implement Bluetooth Smart Audio?
I am trying the Build BLE firmware image from Cypress Psoc 4.1 but having issue in Bootloadable file assignment. Below error: "Error in co...
I am trying the Build BLE firmware image from Cypress Psoc 4.1 but having issue in Bootloadable file assignment.
"Error in component: Bootloadable. The referenced Bootloader is invalid. Verify the Bootloader dependency is correct in the Bootloadable Component, then build project. Invalid bootloader hex file. Unable to read the hex file (C:\demo\bootloader.cyprj.Archive01\bootloader.cydsn\CortexM0\ARM_GCC_493\Debug\bootloader.hex). The path does not exist."
Bootloadable components must have an associated bootloader design to build with. The reference in the Bootloadable's customizer must point to valid *.hex and *.elf files from a Bootloader design."
I am trying to build BLE from command line but since bootloader picking relative path, build process does not go through.
Please suggest me alternative option to build BLE firmware image from command line using cypress Psoc 4.1..