Hi all

For infineon+CYPRESS people.

Are there any plan for releasing PSOC 4200L prototyping kits.

I vote for it😊

Regards

Luis

Dear Sirs and Madams,

The item "Table 3. External Clock Input Requirements" is defined in AN72332, where "Rise time / fall time 3 [ns] (Max)" is specified. 

Please tell us this voltage condition. (For example, 20% -80% VCC, not specified, etc.)

AN72332

https://www.cypress.com/file/122726/download

Regards,

Hi Cypress,

Are there Errata sheets for S25FL064LABNFI043 & CYW43903KUBGT? 

Try to check on your website but unable to found it.

I'm using a CY8CPROTO-063-BLE board. When I try to initialize the BLE ECO clock, Cy_BLE_EcoConfigure() returns CY_BLE_ECO_HARDWARE_ERROR. The proximate cause is a time-out waiting for the  BLE_BLESS_MT_STATUS.BLESS_STATE bit to be set, at line 409 in cy_ble_clk.c.

I have previously had BLE working in both Central Device and Peripheral roles, on two different copies of the board, and both boards now display the same behavior, so it's unlikely actually to be a hardware error. It's almost certainly a configuration problem, but I have no idea where to start looking.

    /* Wait for BLESS in ACTIVE state */
    while(((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) == 0U) && (timeout > 0U))
    {
        timeout--;
        Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
    }
    if(timeout == 0U)
    {
        status = CY_BLE_ECO_HARDWARE_ERROR;
    }

Any suggestions would be appreciated.

Thanks,

-Nick

Hi All.

Our customer going to make Audio device through CYBT-343026-01.
Can i embody A2DP in the Non-OS through CYBT-343026-01?
And Can distribute with Firmware form possible?

Please check this question.

Thank you.

I am confused by the classification of CYBLE-416045 and EZ-Serial Support.  Older posts (2019) claim there is no intention for CYBLE-416045 to support EZ-Serial and I do not see this among listed devices in documentation claiming such support, yet the CYBLE-416045-EVAL I purchased is listed as an EZ-BLE and documentation which comes with the kit references EZ-Serial.  Can you please clarify the standing of this module.  If there is no intention to make this module support EZ-Serial, what is the closest module to it that does (eg, Bluetooth 5 support, number GPIOs, etc.)

Hello,

I am looking for a cross for Adesto's AT25SF041-SSHD-B.

The absolute size can be larger. However, the SPI serial interface and register set have to be exactly the same.

Thank you!

Hello,

I am trying to configure SPI Slave on STM32F4xx in the Laird EWB Platform.  The Host MCU is STM32F412.

I have added SPI4 on the STM32 to the Wiced definitions in platform.c.  I can use this as SPI master without issues.

When I use the Wiced SPI Slave functions, I am getting a build errors.

build/laird.ampnet_app-LAIRD_EWB-ThreadX-NetX-SDIO/libraries/STM32F4xx.a(wiced_platform_common.o): In function `wiced_spi_slave_init':

C:\Data\AMP_WORK\WICED-Studio-6.6\43xxx_Wi-Fi/WICED/platform/MCU/STM32F4xx/../wiced_platform_common.c:429: undefined reference to `platform_spi_slave_drivers'

collect2.exe: error: ld returned 1 exit status

Another developer had the same  issue some years ago. Here is a link to that thread.

SPI SLAVE

The Laird EWB platform has platform_spi_slave_init(...) in the platform file.

...WICED\platform\MCU\STM32F4xx\peripherals\platform_spi.c

This same source file has the functions I used for SPI master. 

What step am I missing to use this source for SPI slave?

Thank you,

-Rocko

Module

  Mfr     : Laird Connectivity

  P/N     : Sterling-EWB

  MCU     : STM32F412VEH6

  WLAN    : BCM4343W Wi-Fi CoB

  Antenna : chip

I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM interface to 40MHz SPI signals and also 40MHz SPI signals sourced from the SPI F-RAM device to signals destined for the x8 parallel SRAM interface. As for the x8 parallel SRAM interface timings, conservatively, I have a memory address setup time of around 250ns, a memory address hold time of around 1250ns and a chip enable hold time of around 750ns ( I'm not quite sure of the timings right now and I know I am missing some timing information for some of the x8 parallel SRAM signals ). I plan on doing this with an ultra-low-power MCU, but, I'd need to use cycle-stretching on the Cypress F-RAM device(s). Is the above kind of conversion doable, especially the cycle stretching?

( N.B. The devices I want to use are one of these : https://www.cypress.com/file/444186/download , https://www.cypress.com/file/444186/download )

Thanks,

jdb2