We are using CY_BLE_EVT_GAP_DEVICE_DISCONNECTED to know if the peripheral got disconnected. On CY_BLE_EVT_GAP_DEVICE_DISCONNECTED we perform connection cleanup, but we noticed on one time the peripheral disconnected but it seems like we missed or didn't get CY_BLE_EVT_GAP_DEVICE_DISCONNECTED.

Is it expected not to get CY_BLE_EVT_GAP_DEVICE_DISCONNECTED event when device disconnect? Is there way to manually check if BLE stack properly disconnected?

Hi,

I worked through the UVC example and got video streaming working.  I then worked through the GpifToUsb example and got data read out working.  Now I am trying to merge them and continuously read out data from an ADC without dropping data.  To do this, I began with the GpifToUsb example and added a simple GPIF project with two threads (0,1):

Next, I added a MANY_TO_ONE auto DMA channel to GpifToUsb:

    //try creating a many to one dma channel
    CyU3PDmaMultiChannelConfig_t dmaMultiConfig;
    CyU3PMemSet ((uint8_t *)&dmaCfg, 0, sizeof (dmaMultiConfig));
    dmaMultiConfig.size           = CY_FX_DMA_BUF_SIZE;
      dmaMultiConfig.count          = CY_FX_DMA_BUF_COUNT;
      dmaMultiConfig.validSckCount  = 2;
      dmaMultiConfig.prodSckId [0]  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_0;
      dmaMultiConfig.prodSckId [1]  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_1;
      dmaMultiConfig.consSckId [0]  = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0);
      dmaMultiConfig.prodAvailCount = 0;
      dmaMultiConfig.prodHeader     = 0;                 /* 12 byte UVC header to be added. */
      dmaMultiConfig.prodFooter     = 0;                  /* 4 byte footer to compensate for the 12 byte header. */
      dmaMultiConfig.consHeader     = 0;
      dmaMultiConfig.dmaMode        = CY_U3P_DMA_MODE_BYTE;
      dmaMultiConfig.cb 			= NULL;
      dmaMultiConfig.notification   = 0;
      //dmaMultiConfig.notification   = CY_U3P_DMA_CB_CONS_SUSP; // CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
      //dmaMultiConfig.cb             = GpifToUsbDmaCallbackMulti;
     
      	  apiRetStatus = CyU3PDmaMultiChannelCreate (&glDmaChHandleMulti, CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE,
              &dmaMultiConfig);
      if (apiRetStatus != CY_U3P_SUCCESS)
      {
          /* Error handling */
          CyU3PDebugPrint (4, "DMA Channel Creation Failed, Error Code = %d\n", apiRetStatus);
          CyFxAppErrorHandler (apiRetStatus);
      }

The result is:

USB event: 11 0
About to connect to USB host
USB event: 0 1
CY_U3P_USB_EVENT_CONNECT detected
CyFxApplnInit complete
USB event: 8 0
USB event: 5 1
setting up dma
              DMA Channel Creation Failed, Error Code = 64

Any idea what I'm doing wrong?  

Hello, I am currently developing a USB PD power bank that utilizes bi-directional 60W input and 100W output. My plan is to use SC8815 I2C bidirectional buck-boost controller for Power and CYPD 3171 as the PD controller. I want to use CYPD3171 to control SC8815 over I2C to configure SC8815 modes(input and output) as well as output and charging voltage, etc. I also want CYPD3175 to inform the main MCU of PD modes, voltages, currents etc. My question is that what is the best way to achieve this functionality? Should I use EZ-PD config utility or PSOC programmer to write the code? Also, how should I upload the program onto CYPD3175, can I use an ST-Link, or use another MCU over I2C? Can someone recommend me a software and programmer combo? I saw this reference design using sc8915 which is extremely similar to my application, and I think I am going to reference the schematic, but I don't see where the code is located, could someone also inform me of where it is located so I can use it as a reference if possible? I am new to the CCG3 ecosystem, thank you very much!

I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM interface to 40MHz SPI signals and also 40MHz SPI signals sourced from the SPI F-RAM device to signals destined for the x8 parallel SRAM interface. As for the x8 parallel SRAM interface timings, conservatively, I have a memory address setup time of around 250ns, a memory address hold time of around 1250ns and a chip enable hold time of around 750ns ( I'm not quite sure of the timings right now and I know I am missing some timing information for some of the x8 parallel SRAM signals ). I plan on doing this with an ultra-low-power MCU, but, I'd need to use cycle-stretching on the Cypress F-RAM device(s). Is the above kind of conversion doable, especially the cycle stretching?

( N.B. The devices I want to use are one of these : https://www.cypress.com/file/444186/download , https://www.cypress.com/file/444186/download )

Thanks,

jdb2

Although ota2 files exist for platform/MCU/STM32F4xx/GCC/STM32F469, I've discovered then read on this site that there is insufficient RAM on the STM family e.g. 384K vs 640K as indicated by the diagram in WICED OTA2 pdf 2.1.2 OTA2 RAM Requirements.

The code size isn't the culprit but the loosing of 200K+ of SRAM.  I tracked it down to:

WICED/platform/MCU/STM32F4xx/GCC/STM32F469/ota2_memory_with_bootloader.ld

/*SRAM             (rwx) : ORIGIN = 0x20000000, LENGTH = 96K*/

SRAM             (rwx) : ORIGIN = 0x20000000, LENGTH = 320K

BTLDR_SRAM       (rwx) : ORIGIN = 0x2004BC00, LENGTH = 17k      /* Boot loader stack at the end. */

/*BTLDR_SRAM       (rwx) : ORIGIN = 0x20010000, LENGTH = 32k      / * Boot loader stack at the end. */

Thanks!

Hi,

I have been working to implement a circuit on PSoC5LP MCU as the PSoC5 LP MCU supports both analog and digital peripherals but in analog we have 4 comparators and 4op-amps, what in the situation if we require MOSFET in the situation, then what should be my approach? 

Anyone Please do let me know, waiting for your reply.

Thanks & Regards,

Prateek

hello,

i've succesfully tried and reproduced the example called "qspi_read_write_using_sfdp".

When i'm importing the rights function in my project, the init function fails (cy_serial_flash_qspi_init).

When i'm digging into the details, it fails when calling Cy_SMIF_MemInit which return CY_SMIF_SFDP_SS0_FAILED

i've compared everything, and i'm not able to find what i'm doing wrong.

is there anybody who experienced the same issue ? thanks

Hello,

I have created a trackpad using the PSoc 4 MCU that will be utilized as a BLE Mouse to control a cursor on a computer screen. I would also like to collect information on the position of the finger on the trackpad. Up until now, I have used the Launch tuner to log this position data, however, I would ideally like this to be done on a computer software. How can change the provided BLE HID Mouse code by Cypress to read information related to the position of the finger on the trackpad rather than the displacement?

Thank you,

I'm looking to interface external memory with one of the PSoC 6 chips. Our application has large storage requirements (to the tune of around 2-4 gigabytes), so SPI NAND is off the table. Since our use case needs bluetooth and possibly USB, we were looking at the PSoC 63 line, but these chips don't seem to support e.MMC memory, which has raised a few questions?

Is there a (relatively) easy way to interface with raw unmanaged NAND using the PSOC 6 line, or to use e.MMC with PSoC 63? Alternatively, is anyone familiar with any chips that could serve as an intermediary SPI Controller to go between a raw NAND chip and the PSoC MCU, or any other way to work around this? 

The PSoC 62 chips seem to have support for SDHC communication, but to use bluetooth and USB I believe we would need one of the CY8C624A/8 chips with two SDHC interfaces. 

Would appreciate any insight on this, as we'll otherwise need to move away from the PSoC chips and start looking at alternatives.

Hello: I have build a downloadable application to be downloaded by a bootloader application over BLE.

Using the CySmart running on PC with dongle I am able to see my bootloader and select it.  Next click firmware update and select my .cyacd2 file to be downloaded.  All steps show OK in the dialog box until Transfer firmware image, then I get this error. see attached. Can anyone tell me how to fix this issue.  Note: both the bootloader and downloadable app were built on the same PSoC creator with the same settings for both projects.

Thanks Brian