Hello!

We have been using the CP62167EV30LL-45BVXI memory on our modules since 2014.

We were affected by the AN66311 in 2014
"TIMING RECOMMENDATIONS FOR BYTE ENABLES AND CHIP ENABLES IN MOBL (R) SRAMS - AN66311"

After this bug was fixed by Cypress and we received new CP62167EV30 components, the error on our modules disappeared.

Until now in 2021.

Memory errors are now increasingly occurring on our assemblies during the final inspection, failure rate approx. 50%. After asking us, we were able to determine that Cypress has changed this SRAM from 90nm technology to 65nm technology.

Hello!

I looked at the data sheet and compared it with the old one and couldn't see any significant changes. An analysis of the memory accesses, timing, etc. on the defective assemblies has not been successful either.

If defective modules from production are equipped with the previous 90nm CP62167EV30LL-45BVXI, then they will function properly again.

Could it be that by changing the technology from 90nm to 65nm, the old bug from AN66311 was redesigned.

I am grateful for a quick answer.

greeting
Max power

Is it possible to convert the Verilog S27KkL0642.v Model into a netlist?

I have been using the S27KL0642.v model very successfully with the Intel Starter ModelSim Simulator.  However, my design has grown to the point that it is very painfully slow.  My design is entirely written in VHDL except for the s27KL0642.v Model.  I also have a copy of Modelsim PE with a VHDL License which run much faster.  I am wondering if I can get a universal netlist version of the S27KL0642 Model that would allow me to use my copy of ModelSim PE with the VHDL License to simulate my design using the netlist version of the S27KL0642 Model instead of the Verilog version??????????????????????

 AMCAP application  unable to display any data on its screen.  On PC side we are able to see data through USB analyser but not on the AMCAP application.

Image sensor: AR1335
AR1335 configured with : RAW8 , 640*480 @ 2FPS and CSI clock-160MHz

CX3 MIPI Configurations :
INPUT video format :        RAW8
OUTPUT video format :    24bit
                                                   640*480 @ 6FPS and CSI clock-160

CyU3PMipicsiCfg_t:
CyU3PMipicsiDataFormat_t dataFormat :      CY_U3P_CSI_DF_YUV422_8_2 (also tried CY_U3P_CSI_DF_RGB888 , CY_U3P_CSI_DF_RGB565_2 )
hResolution =640

CyCx3USBSSConfigDscr:
Number of bits per pixel:            16 (8 bit also tried )
Width in pixel:                                 320 (640 also tried)
0x59, 0x55, 0x59, 0x32,              /*MEDIASUBTYPE_YUY2 GUID: 32595559-0000-0010-8000-00AA00389B71 */
0x00,0x00,0xe1,0x00,            Min bit rate (bits/s):14745600=640*480*8*6
0x00,0x00,0xe1,0x00,            Max bit rate (bits/s):14745600=640*480*8*6
0x00,0xb0,0x04,0x00,           Maximum video or still frame size in bytes(Deprecated)  640*380

CX3- log :
TimeDiff = 10686 ms FPS = 2
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 31 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 32 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 33 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 34 Frm_Sz = 691200 B

With Regards
channabasappa

Dear Sirs and Madams,

I would like to translate AN226137, please confirm to my work.

Regards,
Masashi

AN226137

https://www.cypress.com/file/498626/download

Hello.

Attached project uses 2 PWM components.

PWM makes square wave, and this square wave is stopped or started by PWM_Timer interrupt.

Attached pptx file is waveform of this square wave.

Sometimes it takes some time for voltage level to reach GND when square wave is stopped.

Please confirm red circle of attached pptx file.

Q1)

Could you please let us know reason why this behavior occurs?

Does this behavior occur if PWM is stopped when voltage level is high?

Why doesn't voltage level go to GND immediately?

Q2)

Could you please let us know solution to this behavior?

I want to immediately set voltage level to GND regardless of timing that PWM_stop is called.

Best Regards.

Yutaka Matsubara

Hello, 

We are moving from the cymdhd driver to the brcfmac backport with an CYM43455. We needed to set the following dhd build flags in order to achieve good 5Ghz WiFi throughput. What are the equivalent settings in brcmfmac?

   DHDCFLAGS += -DCUSTOM_AMPDU_MPDU=16
   DHDCFLAGS += -DCUSTOM_AMPDU_BA_WSIZE=64

   DHDCFLAGS += -DCUSTOM_GLOM_SETTING=8
   DHDCFLAGS += -DBCMSDIOH_TXGLOM -DCUSTOM_TXGLOM=1
   DHDCFLAGS += -DDHDTCPACK_SUPPRESS
   DHDCFLAGS += -DRXFRAME_THREAD
   DHDCFLAGS += -DCUSTOM_MAX_TXGLOM_SIZE=31
   DHDCFLAGS += -DMAX_HDR_READ=128
   DHDCFLAGS += -DDHD_FIRSTREAD=128

Thanks!

Hello,

I want to use the iDAC in the CYBLE-222014 and was wondering if the Vref supplies the iDAC. If so,

1) is it okay to supply Vref/iDAC with 5.5V and VDD/VDDR with 2.8V?

2) Also, is it okay to leave Vref disconnected when I am not using any analog blocks?

Hi, 

I made my custom board(FX3 and Camera Module).

I connected it and wrote my custom source code.

The black screen was printed in AMCAP, so I checked the debug message with wireshark.

The Wireshark confirmed that the data was output.

The resolution is 340(W) x 260(H), 30fps and 12bit data output.

You can see data in wireshark log.

• wireshark log  => ((16380 * 10) + 13292=177,092     
• resolution  =>  340*260*2 = 176,800
• difference => 177,092 - 176,800 = 292
• As above, additional buffers are entered, and it is necessary to check if there is a problem with the code.

I tried to change DMA Buffer size(CY_FX_EP_BULK_VIDEO_PKT_SIZE and CY_FX_EP_BULK_VIDEO_PKTS_COUNT ) in uvc.h

If i change buffer size, the buffers in the data packet are output differently.

Regards,

Jay