We are using CY_BLE_EVT_GAP_DEVICE_DISCONNECTED to know if the peripheral got disconnected. On CY_BLE_EVT_GAP_DEVICE_DISCONNECTED we perform connection cleanup, but we noticed on one time the peripheral disconnected but it seems like we missed or didn't get CY_BLE_EVT_GAP_DEVICE_DISCONNECTED.

Is it expected not to get CY_BLE_EVT_GAP_DEVICE_DISCONNECTED event when device disconnect? Is there way to manually check if BLE stack properly disconnected?

I'm trying to send data packets between two BLE devices (A and B) with both peripheral/central GAP roles.  When I add and remove other devices to the BLE network, I find by debugging device A that it can enter a state where any attempt at sending a GATT notification to device B returns a  CY_BLE_ERROR_INVALID_OPERATION error, though it can send GATT notifications to other devices that are connected.  In this circumstance, A is peripheral wrt to device B, and GATT write requests can be sent from device B to device A.  Cypress code comments indicate CY_BLE_ERROR_INVALID_OPERATION occurs when the BLE stack queue is full or some other problem occurs.  Is it possible to look at the BLE stack queue in debug mode to get a clearer idea of what's going wrong?

I have an Psoc63 as BLE 5 central and three PSoC 4200 as BLE 4.2 peripheral. After a successful discovery from central using whitelist I try to connect to one of the three peripheral using his address.  Unexpectedly the central was connected with a peripheral with different address!!!!! Also I try an unexisting address and again it was connected with a random peripheral with different address. Maybe the issue arise from the BLE 4.2 peripherals.

I will appreciate your help to this

Hello, I am currently developing a USB PD power bank that utilizes bi-directional 60W input and 100W output. My plan is to use SC8815 I2C bidirectional buck-boost controller for Power and CYPD 3171 as the PD controller. I want to use CYPD3171 to control SC8815 over I2C to configure SC8815 modes(input and output) as well as output and charging voltage, etc. I also want CYPD3175 to inform the main MCU of PD modes, voltages, currents etc. My question is that what is the best way to achieve this functionality? Should I use EZ-PD config utility or PSOC programmer to write the code? Also, how should I upload the program onto CYPD3175, can I use an ST-Link, or use another MCU over I2C? Can someone recommend me a software and programmer combo? I saw this reference design using sc8915 which is extremely similar to my application, and I think I am going to reference the schematic, but I don't see where the code is located, could someone also inform me of where it is located so I can use it as a reference if possible? I am new to the CCG3 ecosystem, thank you very much!

Hi,

Can we just implement TPS25982 block diagram to PSoC5LP MCU. I am attaching the link for datasheet of TPS25982 and the functional block diagram

 https://www.ti.com/lit/ds/symlink/tps25982.pdf?ts=1611299035488&ref_url=https%253A%252F%252Fwww.google.com%252F

Page No:18

Please do let me know in full brief about the different blocks.

Hello，

I am learning PSoC6 from the PSoC6 101 video tutorial series . From the PSoC 6 - 1-1-Introduction Alan Hawse told that PSoC6 chapters contains 4 parts.
I have downloaded the 1st,2nd and 3rd parts. And the last part is "connecting with WiFi & Cloud services".And I do not know the hyperlink of it. How can I get it?
Thanks in advance.

Hello,

  We have custom board with a 43012 connected via SDIO to a Xilinx ZynqMP.    We are using the latest Xilinx release which run the 5.4.0 kernel.   Based on information in the v5.4.18-2020_0625 version of the backport driver and cypress-yocto-scripts I have added support into yocto to build everything.

  I am using the following firmware/nvram files:

BCM43012C0_003.001.015.0102.0141.1LV.hcd*  brcmfmac43012-sdio.1LV.txt  cyfmac43012-sdio.bin  cyfmac43012-sdio.clm_blob

I get the timeout error so the wlan0 interface is never created.

Based on the kernel logs the chip is powered up and the driver can talk to it.

================================================================

[   12.985101] brcmfmac: brcmf_sdio_kso_init Enter

[   12.985117] brcmfmac: brcmf_sdio_drivestrengthinit No SDIO driver strength init needed for chip BCM43012/2 rev 2 pm0

[   12.985353] brcmfmac: brcmf_sdio_probe completed!!

[   12.985359] brcmfmac: brcmf_fw_alloc_request: using cypress/cyfmac43012-sdio for chip BCM43012/2

[   12.994144] brcmfmac: brcmf_fw_get_firmwares enter: dev=mmc1:0001:1

[   12.994149] brcmfmac: brcmf_ops_sdio_probe F2 init completed...

[   12.994254] usbcore: registered new interface driver brcmfmac

[   13.000643] brcmfmac: brcmf_fw_complete_request firmware cypress/cyfmac43012-sdio.bin found

[   13.000692] brcmfmac mmc1:0001:1: Direct firmware load for cypress/cyfmac43012-sdio.xlnx,zynqmp.txt failed with err2

[   13.011657] brcmfmac: brcmf_fw_complete_request firmware cypress/cyfmac43012-sdio.txt found

[   13.011662] brcmfmac: brcmf_fw_request_nvram_done enter: dev=mmc1:0001:1

[   13.011690] brcmfmac: brcmf_nvram_handle_key warning: ln=33:col=10: '=' expected, skip invalid key entry

[   13.011788] brcmfmac: brcmf_fw_request_nvram_done nvram 00000000d6229003 len 2356

[   13.011796] brcmfmac: brcmf_sdio_clkctl Enter

[   13.011798] brcmfmac: brcmf_sdio_htclk Enter

[   13.011849] brcmfmac: brcmf_sdio_htclk CLKCTL: turned ON

[   13.011852] brcmfmac: brcmf_sdio_clkctl 1 -> 3

[   13.011856] brcmfmac: brcmf_sdio_download_firmware firmware rstvec: 0

[   13.011858] brcmfmac: brcmf_sdio_download_code_file Enter

.

.

[   13.070357] brcmfmac: brcmf_sdio_download_nvram Enter

[   13.070399] brcmfmac: brcmf_sdiod_ramrw write 2356 bytes at offset 0x000076cc in window 0x00098000

[   13.070581] brcmfmac: brcmf_sdio_verifymemory Compare RAM dl & ul at 0x0009f6cc; size=2356

[   13.070586] brcmfmac: brcmf_sdiod_ramrw read 2048 bytes at offset 0x000076cc in window 0x00098000

[   13.070711] brcmfmac: brcmf_sdiod_ramrw read 308 bytes at offset 0x00007ecc in window 0x00098000

[   13.070755] brcmfmac: brcmf_chip_set_active Enter

[   13.071159] brcmfmac: brcmf_sdio_clkctl Enter

[   13.071161] brcmfmac: brcmf_sdio_htclk Enter

[   13.071177] brcmfmac: brcmf_sdio_htclk CLKCTL: turned OFF

[   13.071180] brcmfmac: brcmf_sdio_clkctl 3 -> 1

[   13.071185] brcmfmac: brcmf_sdio_clkctl Enter

[   13.071187] brcmfmac: brcmf_sdio_htclk Enter

[   14.072857] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (1000000): clkctl 0x50

[   14.080236] brcmfmac: brcmf_sdio_clkctl 1 -> 1

[   14.080244] brcmfmac: brcmf_sdio_firmware_callback failed: dev=mmc1:0001:1, err=0

[   14.080268] brcmfmac: brcmf_ops_sdio_remove Enter

======================================================================

It appears that the firmware is loaded and the nvram.  However, after the nvram is loaded and this code from brcmf_sdio_htclk is executed I get the timeout error.

/* Otherwise, wait here (polling) for HT Avail */

timeout = jiffies +

  msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);

while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {

  clkctl = brcmf_sdiod_readb(bus->sdiodev,

   SBSDIO_FUNC1_CHIPCLKCSR,

   &err);

  if (time_after(jiffies, timeout))

    break;

  else

   usleep_range(5000, 10000);

  }

  if (err) {

    brcmf_err("HT Avail request error: %d\n", err);

    return -EBADE;

  }

  if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {

    brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",

      PMU_MAX_TRANSITION_DLY, clkctl);

   return -EBADE;

}

It looks like the the code is trying to re-initialize certain things after loading the nvram and what looks like a status register, SBSDIO_FUNC1_CHIPCLKCSR, has an error it it.

Any ideas of what could be happening here?  Is this process trying to switch from an internal to external clock?   We do have an external osc. connected to EXT_LPO.  I know it's unlikely, but is there any available documentation that would describe SBSDIO_FUNC1_CHIPCLKCSR?

thanks

jeff

Hello,

I am using PSOC6 PROTOTYPEKIT BOARD 。
I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3
The Screenshot in PSOC Creator 4.3.

The errors occurred in building
It seems that the PSOC Creator 4.3 cannot interpret the line 171

Can't handle expression 'Z' in the final equation for 'org_data(0)'.

And I do not know how to solve it.

And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.

Thanks in advance.

I checked the datasheet and website in search of ESD information and could not find any specific to P/N S25FL064LABNFI011. I would like to obtain ESD Voltage Rating Information for HBM per JEDEC JS-001 and CDM per JEDEC JESD22-C101 on the following device P/N S25FL064LABNFI011. Thanks.