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I have many kitprog (ver1) from ther CY8CKIT-059, These have been broken off from the kit. The kitprog does not have connectivity to the SWD or JTAG...
I have many kitprog (ver1) from ther CY8CKIT-059, These have been broken off from the kit. The kitprog does not have connectivity to the SWD or JTAG pins, so the only method of programming the kitprog is by using the bootloader installed from the programmer. As custom bootloader may resolve my issue below but I can't change the bootloader.
The issue is I can successfully bootload host a custom program many times successfully, but then later when adding functionality to the bootloadable program I get an bootloader host downloading issues that prevent downloading.
I am assuming the original kitprog has not been verified correctly and there is an incompatibility. I do have a couple questions that maybe someone can answer that has been though this issue,
I am using the kitprog hardware (not 2) with the latest software 2.2.1 The cy9ckit-059 says this needs to be 2.20 or later. The documents for the original kitprog user manual (ver-I 2018) says the bootloadable needs to start its program at 0x0002800. However the newest kitprog2 user manual has the starting address for bootloadables at 0x0003200. Is it possible to findout the flash size of the locked part for kitprog and kitprog2?
This value is need to use the kitprog for custom applications, but only cypress has accessibility to the kitprog and kitprog2 source.
Trying to network BLE devices configured in both central/peripheral roles. A connection problem occurs (infrequently) whereby a peripheral will conne...
Trying to network BLE devices configured in both central/peripheral roles. A connection problem occurs (infrequently) whereby a peripheral will connect to a central device and then immediately disconnect (before CY_BLE_EVT_GAPC_SCAN_PROGRESS_RESULT is called). Disconnect reason 62 is given. Timing the connect / disconnect events shows there is ~140ms between them, and since the min/max connection intervals are set to 20/30ms on all devices, this suggests the peripheral/slave is not responding to the central/master connection attempts immediately after first connection. The devices are very close together and there does not seem to be an rssi problem. I've removed most additional code that I thought could be interfering with the timing of BLE event processing. Any suggestion on what the problem might be and/or how to debug it?
We've developed a product using CYBLE-012011-00 module and in the end, we paid the qualification process etc.After two years we realized about ...
We've developed a product using CYBLE-012011-00 module and in the end, we paid the qualification process etc. After two years we realized about the missing CAPTRIM configuration register and of course the malfunction that it makes. It is possible to have a checklist of all the things it needs to be covered to be sure that problems like this one do not happen again?
I'm developing some more products now with OTA to try to overcome future problems but even so, I want to prevent them.
There is also information about all the steps to put the product on the market without any issues in the future? Thanks! BR,
I'm trying to adapt this code example to our design requirements. We are currently running this code example on PSoC 6 BLE prototyping kit (CY8CPROTO-...
I'm trying to adapt this code example to our design requirements. We are currently running this code example on PSoC 6 BLE prototyping kit (CY8CPROTO-063-BLE). I've switched the BLE stack to running on Cortex M0+ following the instructions and changed the toolchain to MDK. However we encounter HardFault during App2 startup, in the Cy_BLE_Start function. Our observations are:
This issue does not occur when using ARM-GCC toolchain
App1 (DFU mode) works properly
With the debugger we were able to trace down the HardFault to function Cy_BLE_StackInit, and from the stack frame the PC register address when the fault occurred belongs to the function CyBle_RcbRegRead
Our FPGA may send variable length data(4B~16kB, integral multiple of 4Bytes) to FX3 in which firmware runs as slave FIFO mode, host app invoke ...
Our FPGA may send variable length data(4B~16kB, integral multiple of 4Bytes) to FX3 in which firmware runs as slave FIFO mode, host app invoke XferData() to initiate a BULKIN transfer for reading data stored in FX3.
At each BULKIN event initiated by host, a certain len parameter must be passed into XferData() refer to Cypress CyAPI Programmer's Reference, for example 16384, if actual length of packet which sent by FX3 is shorter than 16384(ie partial packet), will XferData() receive the short length packet and return ture or return false for time-out? if this function can receive short packet, where can i get the actual length after the XferData() executed ?