Dear Cypress Community,
I am using an evaluation board for PSoC 5LP (CY8CKIT-059) and trying to downmix a signal.
My aim is to downmix a noisy signal that contains a very small sine wave (1mVpp) whose frequency is known, e.g., 10 MHz. The DC value I would get after the mixing+filtering tells me if that sinewave is present in the signal or not.
I was able to achieve this only for sine waves of max. 4 MHz using the mixer component of 5LP.
Question: Is it possible to mix with a frequency higher than 4 MHz so that I can downmix a 10 or 15 MHz signal?
I ask this because I do not want to include/pay a separate (I-Q) demodulator in my design.
My customer, Christie Digital, uses an old PSOC1 in their KVM project. However, they copied and pasted this design into a newer design and now they want to update the FW in the PSOC1 and do debug. But, I don't think they have the old PSOC1 ICE-cube and the cable to do the work :-(. I think they wanted this old Eval board: CY3215A-DK In-Circuit Emulation Lite Development Kit. But, I don't think this is made anymore. This from the customer:
CY3215A-DK In-Circuit Emulation Lite Development Kit has an ICE-cube that could be directly plugged into our CY8C28 Processor Module that comes with CY8CKIT-001. Even though the processor numbers do not match, CY8C28 is still a member of PSOC1 family, so we could utilize it to do checks with CY8CKIT-001 (then there is no need to soldering a pod on the PCB of our product). Someone at Cypress probably has them in some dusty boxes somewhere. We also need the flat cable (from the CY8CKIT-001 User Manual)
Can the fork() and pipe() function be used with the PSOC 5LP? I seem to get undefined reference when using them although they are declared. I realize PSOC 5LP is not multi-CPU but I have a function that blocks my loop and I don't really care if it takes a while to execute. Just need to fire it off from within my loop.Show Less
Is there a way to modify an existing component cy_lfclk?
I can import it on the components tab, I can change the code. But I can't figure out how to connect it to the project?
How to replace a component in a project with a modified one?
I have a couple of CY8CKIT-059 boards. I broke the kitprog off of one of them and have been using it to program things. I want to use its virtual com port uart capability with 12.6 and 12.7 on J9 of the kitprog. however, it never enumerates as a virtual com port. I plugged in a non-separated cy8ckit-059 and the virtual com port appears in my device manager and terminal program. then, I went to the PSOC Programmer program (version 3.27.1) and the broken-off kitprog shows up in there as "KitProg (CMSIS-DAP/251530)" with a version of "CMSIS-DAP VERSION 1.0" while the non-broken-off one shows up as "KitProg/0f20183201324400" and says it is using kitprog version 2.20.
why is this separated kitprog acting different/weird? how can I get it back to a regular kitprog?Show Less
I purchased the devkit for the CYBT-343026-01 modules (CYBT-343026-EVAL) and was able to use it for my specific needs (run it in SPP mode) in an instant. Consequently I used the module in a design (replicated the evaluation board's schematic), received the boards, but the modules will not communicate through the PUART which leaves me unable to send/receive HCI commands for configuration. On top of that the name of the Bluetooth device is "MTK DUT 706" which is different from what the datasheet says.
I have not found anything related to this online and I am starting to be suspicious that there is a problem with the factory firmware.
In one design we use the SRAM CY62167EV30LL-45BVXI with 65nm technology.
The data sheet CY62167EV30_MOBL_16_MBIT_1M_X_16_2M_X_8_STATIC_RAM.pdf says
"The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. "
A date is read from an address from the FLASH and this date is stored in the same address in the SRAM. Then the address will not be toggled.
Is it possible during this process that the SRAM goes into automatic power down?
How is the timing for the required address toggling defined?
The case would be very bad if the same address in the SRAM was written several times with different dates in succession. The SRAM is permanently chipselect with /CE1 and write is / WE controlled.
The last date is then not written because the SRAM has gone into power down due to the missing address toggling.
The SRAM can only be powered up again with a chip select /CE1=0 to 1 to 0.
Are 2 write commands possible in succession on this SRAM?
Hence my question about the time in ns at which the address must absolutely change so that the SRAM does not go into power down. This time is not in the data sheet. /CE1 is permanently low.
With best regards
In KBA210620 you say that 22Ohm resistors should be placed in series with the D+ and D- USB data line but the technical reference manual specifically says that the silicon has 22Ohm resistors internal to the chip:
The PSoC USB has these features:
■ Integrated 22 USB termination resistors on D+ and D– lines, and 1.5-k pull-up resistor on the D+ line
Do I need external 22Ohm resistors as well?
KBA210620 also says that 0.1uF should be connected between VBUS and GND. Is this necessary even if VBUS is just used to sense the presence of the host, and enable the USB drivers? There is no reference to this in the trm.
I am having problems getting the USB to work reliably. It works as long as there is at least one USB hub between the PSOC and host controller on the PC, but not if the PSOC is connected directly to the host controller, either USB3 or USB2. Error message is : "USB device not recognised, the last device connected to this computer malfunctioned and windows does not recognise it" with device manager saying "Windows has stopped this device because it has reported problems. (Code 43). A request for the USB device descriptor failed."
Traces on the PCB between USB connector and PSOC are about 5mm in length, matched to about 0.5mm, and reasonably matched to 100 Ohms. PSOC is self powered.