Hello,

For my project, I'm currently using the FX3 (CYUSB3014) and looked into the SPI GPIO bit banging example as reference for the bit banging approach and given my timing requirements, it seems that we would need a delay less than a microsecond in between bits. From the looks of it, the smallest delay that can be used is with the CyU3PBusyWait (1uS). Is it possible to sample the logic levels of the GPIO pin/s with smaller delays and perform bit banging at a faster rate?

Thanks

In my application Psoc4 has to serve a device that could be configured  in SPI or parallel mode during runtime. In SPI mode pin named D0 has to be configured as MTSR, D1 has to be configured as SS,  D2 has to be configured as SCLK and  D3 has to be configured as MRST. In parallel mode  D0...D3 are part of the parallel IO (D0...D7) offering bidirectional IO. How to implement this switch on the fly?

For CYW920719B2Q40EVB-01, using ModusToolbox 2.2,

While trying to build the "empty_project", I get a build error that it can not link to the elf file. Build output is attached.

It is not building the elf file for the empty project. I have no idea why or even where to check the specification that it build the elf file.

Full error log attached. Per the help, this should build "out of the box" with no changes and do something simple, but it doesn't. ALL other projects build just fine, this is the ONLY one that doesn't.

>>>

Compiling V:/Software/MedPatch/MedPatchPer/template/empty_wiced_bt/build/CYW920719B2Q40EVB-01/generated/lib_installer.c  -DWICED_BT_TRACE_ENABLE -DWICED_HCI_TRANSPORT_UART=1 -DWICED_HCI_TRANSPORT_SPI=2 -DWICED_HCI_TRANSPORT=1  -DHCI_UART_MAX_BAUD=4000000 -DHCI_UART_DEFAULT_BAUD=3000000 -DSS_LOCATION=0x500000 -DVS_LOCATION=0x501000 -DDS_LOCATION=0x503000 -DDS2_LOCATION=0x582000 -DCYW20719B2=1 -DBCM20719B2=1 -DBCM20719=1 -DCYW20719=1 -DCHIP=20719 -DAPP_CHIP=20719 -DOTA_CHIP=20719 -DCHIP_REV_A_20719B2=1 -DCOMPILER_ARM -DSPAR_APP_SETUP=application_setup -D__TARGET_CPU_CORTEX_M4 -D__ARMCC_VERSION=400677 -DPLATFORM='"CYW920719B2Q40EVB_01"' -DWICED_SDK_MAJOR_VER=2 -DWICED_SDK_MINOR_VER=5 -DWICED_SDK_REV_NUMBER=0 -DWICED_SDK_BUILD_NUMBER=7341 -g3 -DSPAR_CRT_SETUP=spar_crt_setup -DCOMPONENT_SOFTFP -DCOMPONENT_bsp_design_modus -DCOMPONENT_gatt_utils_lib -DCOMPONENT_hidd_lib -I. -I../../../dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/COMPONENT_bsp_design_modus -I../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/COMPONENT_bsp_design_modus -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/baselib/20719B2/include -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/baselib/20719B2/include/hal -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/baselib/20719B2/include/internal -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/baselib/20719B2/include/stack -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/baselib/20719B2/internal/20719B2 -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01 -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/../../../dev-kit/btsdk-include -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/WICED -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/WICED/common -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/include -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/include/arm -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/include/arm/cmsis -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/include/hal -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/include/internal -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/include/stack -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/internal -I./../../../wiced_btsdk/dev-kit/baselib/20719B2/internal/20719B2 -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01 -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/baselib/20719B2/include -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/baselib/20719B2/include/arm/cmsis -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/baselib/20719B2/include/hal -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/baselib/20719B2/include/internal -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/baselib/20719B2/include/stack -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/baselib/20719B2/internal/20719B2 -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01 -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/../../../dev-kit/btsdk-include -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/COMPONENT_bsp_design_modus -I./../../../wiced_btsdk/dev-kit/bsp/TARGET_CYW920719B2Q40EVB-01/COMPONENT_bsp_design_modus/GeneratedSource -I./../../../wiced_btsdk/dev-kit/btsdk-include -I./GeneratedSource

    Linking output file EmptyWicedBluetooth.elf

collect2.exe: error: ld returned 1 exit status

make[1]: *** [../../../wiced_btsdk/dev-kit/baselib/20719B2/make/core/build.mk:470: V:/Software/MedPatch/MedPatchPer/template/empty_wiced_bt/build/CYW920719B2Q40EVB-01/Debug/EmptyWicedBluetooth.elf] Error 1

make: *** [../../../wiced_btsdk/dev-kit/baselib/20719B2/make/core/main.mk:350: secondstage] Error 2

"C:/ModusToolbox/tools_2.2/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_MAKE_IDE_VERSION=2.2 CY_IDE_TOOLS_DIR=C:/ModusToolbox/tools_2.2 -j8 all" terminated with exit code 2. Build might be incomplete.

Hi all,

We have a CY8CKIT-064S0S2-4343W kit that we're trying to get up and running with the demonstration code that is generated from AWS. I'm following the getting started guide located here https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_cypress_psoc64.html and have successfully done everything up to the point of getting working code.

I've managed to build and flash the provided demo application, and the board successfully boots but then halts shortly after with "ERROR: stack overflow" — the attached screenshot shows what is happening. This happened with no WiFi credentials set, I then tried to set WiFi credentials and the error still happened. 

Any help in resolving this issue would be appreciated!

I want to check the failure mode of the MCU to comply with IEC60335 (safety standard).

Please let me know if any of the following failure modes of the S6E2H14 port are not considered (it is considered that they will not occur).

1) High sticking
2) Low sticking
3) Sticking to intermediate potentials other than High / Low
4) Randomly fluctuates (High / Low switches randomly)

Also, are there any other port failure modes that are considered?

Thanks,
Tetsuo

I am interested in designing a solution for measuring TDS (Total Dissolved Solids) in water and sending the data over the 12V power line to the receiving end where the data is displayed.

I remember using a PSoC for power line communication a long time ago before the PSoC PLC version was released.

If I want to combine using a PSoC for both TDS and PLC, which PSoC do you recommend?

Thank You,

Steve

hi all, 

I am using CYBLE 012011-001 module, where i configured ADC as given in code example of battery_level_01. But, in results, getting constantly a fixed value. I think ADC is not working. I have configured ADC as, Vref is internal VREF, fixed resolution, clk freq is 1000khz & enable ADC interrupt in which i have took converted result. Constant value(883 something) has been appearing at maximum input of battery. 

Please suggest me if anything is going wrong or what should i do next to ADC to be work? 

There is a phenomenon that the voltage drops to 1V for about 400ms during OS boot. It occurs on both the created board and CY4608.

Attach the waveform.

ch1 (yellow): U4 Pin1 (nENP1)
ch2 (blue): VBUS

My perception is that a reset is issued to the hub when the OS USB driver is initialized, and the HX2VL receives it and controls the Enable signal of the power supply IC. Is it correct? If yes, is this behavior as specified? Is there a time limit for making the Enable signal Inactive?

Thanks,
Tetsuo

Dear Sirs and Madams,

We were introduced to the SiT which is a transmitter that meets the needs of the HX2VL.

Please refer to the solution at the URL below.

https://community.cypress.com/t5/USB-Hosts-Hubs-Transceivers/CY7C65642-Rise-time-fall-time-specification/m-p/263645#M2052

When We measured the RMS Jitter of SiT8008,
The measured value was 589.4 [ps] at BW 10-5MHz.

According to Cypress application note AN72332
Jitter (RMS): 260 [ps (Max)]

It seems that the above specifications are not met, is that okay?

Could you comment about this result?

Regards,